Two processors A and B share the same bus, as shown below: The bus is capable of transferring l…

Two processors A and B share the same bus, as shown below:

The bus is capable of transferring l byte (either from or to memory) every 500 ns. For a particular instruction mix, the average instruction executed is 1 byte long and causes three additional bus transactions: two reads and one write. The detailed instruction timing for both processors is as follows:

To improve the performance of the system, a cache is added to processor B:

Two caches are proposed. Cache 1 has a hit ratio of 80 percent and a cache access time of 100 ns; cache 2 has a hit ratio of 90 percent and a cache access time “of 200 ns. (Cache access time is the access time to a datum when a cache hit occurs; it includes all decoding and searching time to determine if the datum was in the cache.) Assume that no overhead is imposed by the cache when a cache miss occurs, and ignore the effects of write-through or copying of data into the cache after a cache miss. Which cache should be used? Consider both the effect on the speed of execution of instructions on processor B and the effect on the average bus loading (which will affect the execution speed of processor A). Give an argument in favor of your choice and justify your argument with numerical performance figures.