Show how you would write nanocode for the move microinstruction to take advantage of the new circuitry introduced in problems 12.17 and 12.18.
Looking for a way to activate the new data path you designed in problem 12.17 in parallel with the execution of another nano instruction, you spy an N.C. (not connected) control-ROM output bit. Show how, with only a single added gate, this ROM output bit could be used to activate the new data path (that is, load the OP register and clear the phase counter). Your change should be compatible with the original nanocode; in other words, the assertion of LDOP should still cause the OP register to load and the phase counter to clear. (Note that the original nanocode always drives the N.C. pin high.)
You are examining the MAYBE hardware and nanocode to see if you can prefetch microinstructions in parallel with other computation. In the control-ROM listing you notice three things: The last phase of every microinstruction’s nanocode always contains the nano instruction Qp code c– PROM; ADR+. The second-to-last phase of every microinstruction’s nanocode usually contains an instruction that does not read from the microcode ROM. The OP register is never loaded from anywhere except the microcode ROM. You figure that most of the time, the OP register could be loaded simultaneously with the heretofore second-to-last nano instruction phase, instead of taking an additional clock cycle. You realize that for this to happen you must provide an additional path on which data can flow from the PROM to the opcode register, simultaneously with whatever data are being transferred on the data bus during the last op code’s final phase. Before actually changing the nanocode, however, you work out the details of this new data path. Using only eight three-state buffers and no other gates, show how to modify the MAYBE hardware to provide a dedicated data path between the microcode ROM and the OP register. (In the resulting machine, the OP register will be loadable only from the microcode ROM; it will no longer be loadable from the data bus.) The resulting circuit must still work with the old nanocode and will not yet provide any performance gain. (Note that while the OP register is never loaded from anywhere except the PROM, the PROM is sometimes used as a source for other destinations. Thus it must still be able to drive the data bus when is asserted.)