A computer architect is tasked to design an adder such that it would complete the addition of…

Question 4: A computer architect is tasked to design an adder such that it would
complete the addition of 32 bits within 200ns. And that the adder should have an
area less than 1000 µm2
. Given that he can use the following blocks: (4 points)
Block Delay (ns) Area (µm2
)
FA- Type 1 7 20
FA- Type 2 4 40
pi & gi generator for 32-bits 50 (time includes generating carry) 250
* There is no hardware available to generate Super Pi or Super Gi.
* Assume you can’t mix FA’s inside the same adder.
1) What is the type of the Adder that he should design? (CPA, CLA-1, CLA-2)
2) From the given list, what components he/she would need in his design?
3) What is the total area of the design?
4) What is the total delay of the proposed design?